FPGA - in - the - Loop Implementation of an Adaptive Matrix Inversion Algorithmic Co - Processor : An Embedded Dual - Processor System

This article presents a comprehensive and efficient modelbased technique on how algorithms can be developed, synthesized, modeled, preverified and implemented on embedded processors platforms which consist of a personal computer and a field programmable gate array (FPGA). To illustrate the proposed technique a new adaptive matrix inversion algorithm is proposed and used. The algorithm is first implemented as a synthesizable streamingloop floatingpoint MATLAB programs. The MATALAB programs are then synthesized using Xilinx AccelDSP to generate a System Generator block model equivalent of the MATLAB programs. Using the generated System Generator block model, the Xilinx System Generator for DSP is then employed to develop a complete System Generator hardware model of the adaptive matrix inversion algorithm. A FPGAintheloop cosimulation and preverification using a generated hardware cosimulation block model is carried out for performance comparison. Next, an embedded MicroBlazeTM processor system is designed, tested and imported into a System Generator hardware model of the adaptive matrix inversion algorithm inside MATLAB/ Simulink environment; and a complete FPGAintheloop implementation is performed. The FPGAintheloop simulation results are presented. Conclusions drawn from the study are given together with some discussions and directions for further work.